Author: Rachelle Trent
The migration from parallel to serial interfaces is not a new idea to enterprise and storage applications. These storage interface technologies have turned to a serial approach because parallel implementations have become a performance bottleneck.
Parallel buses suffer from many undesired analog effects such as crosstalk, ground bounce, ringing/reflections and clock skew. Pushing parallel technologies to higher and higher speeds intensifies these analog symptoms and places major constraints on designs that must maintain backwards compatibility to legacy parallel technology.
The new standard, Serial Attached SCSI (SAS), is the evolution of the SCSI interface from a 16-bit parallel bus approach (Ultra320 SCSI) to a differential serial link running at 3.0 Gb/s. SAS is being introduced at 3.0 Gb/s and has a planned roadmap up to 12 Gb/s over the next several years.
To alleviate many of the design problems associated with high-speed parallel buses, Serial Attached SCSI (SAS) uses low-voltage differential signaling. Low-voltage differential signaling requires each signal to be transmitted over two wires. The first wire carries the signal itself (+) and the second wire carries the inverse (-) of the signal, as shown in Figure 1.
The receiving device decodes the signal based on the differential voltage between the two wires and ignores any common DC voltage between the two wires. Any noise injected into the serial link will be common to both wires and will be filtered out as common mode voltage. In addition, any drift in the DC voltage of two wires will also not affect the receiver’s ability to decode the signal. One benefit of a differential signaling approach is excellent immunity to noise when compared to a high-speed parallel bus.
Figure 1: High Speed Serial Link Topology
Migrating from a high-speed parallel bus to a high-speed differential serial link implementation has significant impact on the number of physical wires required for connection between two devices. For a full duplex link, Ultra320 SCSI requires 64 connections whereas SAS only requires four connections. The drastic reduction in the number of connections required allows for smaller connectors and simplifies routing. New compact connectors and routing ease will enable a new generation of dense devices such as small form factor (2.5″) hard disk drives as illustrated in Figure 2.
Figure 2: Small Form Factor Disk Drives using SAS
SAS does not require a separate signal line dedicated for a clock as in Ultra320 SCSI. In serial interfaces, the clock is embedded in the data stream. The receiver circuitry has the built-in ability to extract the clock from the transmitted data and continuously track the clock. As a result, the serial link does not suffer from clock skew problems prominent in high-speed parallel bus approaches.
One of the most significant advantages of a high-speed serial interface is the point-to-point connection topology. Each host or source is connected directly to the target or destination. Each link operates independently with no sharing of bandwidth. In addition, the point-to-point nature of the link ensures that there is only one receiver on the link and that the receiver is located at the endpoint of the transmission line. In this configuration, near perfect termination is possible and unwanted reflections are eliminated. In the SCSI parallel bus approach, two target devices can be attached to a parallel bus as shown in Figure 3. This configuration degrades the termination of the data path resulting in large reflections as the bus speed is increased.
Figure 3: (a) Shared Bus Bandwidth in SCSI, (b) Point-to-Point Dedicated Serial Links for SAS.
Serial interconnect technology provides several performance advantages over parallel interconnect including point-to-point connections for full bandwidth operation and lower required pin count, enabling small form factors and more dense systems. It is important to note that designers must carefully examine board materials and apply proven techniques for high-speed board layouts to achieve optimum performance of high-speed serial links. For more information on designing with high-speed serial links, please refer to http://www.pmc-sierra.com/pressRoom/whitePapers.html for a white paper entitled “Designing Multi-Gigabit Serial Backplanes with High Speed Serial Solutions.”